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cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 1/12 ctk24bc01-16q8 cy s t ek product s pecification 2-wire serial eeproms 1k/2k/4k/8k/16k ctk24bc01-16q8 description the ctk24bc family provides 1k, 2k, 4k, 8k and 16k of serial electrically erasable and programmable read-only memory (eeprom). the wide vdd range allows for low-voltage operation down to 1.8v. the device, fabricated using traditional cmos eeprom technology, is optimized for many industrial and commercial applications where low-voltage and low-power operation is essential. the device is accessed via a 2-wire serial interface. features ? internally organized as 128 8(1k), 256 8(2k) ? 100khz(1.8v)& 400khz(5v) compatibility 512 8(4k), 1024 8(8k), 2048 8(16k) ? bi-directional data transfer protocol ? low-voltage and standard-voltage operation : ? self-timed write cycle (5ms max) 1.8 ~ 5.5v ? write protect pin for hardware data protection ? 2-wire serial interface bus ? 8-byte page (1k, 2k) and 16-byte page (4k, 8k, 16k) ? date retention : 100 years write modes ? high endurance : 1,000,000 write cycles ? allows for partial page write absolute maximum ratings parameter ratings unit voltage on any pin with respect to ground -0.8 to v cc +1.5 v maximum operating voltage 6.25 v dc output current 5.0 ma operating temperature range -55 ~ +125 storage temperature range -65 ~ +150 note: stresses beyond those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at thes e or any other conditions beyond those indicated in the operational sections of these specifications are not implied. exposure to absolu te maximum rating conditions for extended periods may affect device reliability. http://
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 2/12 ctk24bc01-16q8 cy s t ek product s pecification pin configurations pin name function a0-a2 address inputs sda serial data scl serial clock input wp write protect gnd ground v cc power supply block diagram
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 3/12 ctk24bc01-16q8 cy s t ek product s pecification pin descriptions serial data(sda) : the sda pin used for sending and receiving data bits in serial mode. since the sda pin is defined as an open-drain connection, a pull-up resistor is needed. serial clock(scl) : the scl input is used to synchronize data input and output with clocked out on the falling edge of scl. device/page addresses(a 2 , a 1 , a 0 ) : the a 2 , a 1 , and a 0 pins are used to address multiple devices on a single bus system and should be hard-wired. the ctk24bc01 and ctk24bc02 use the a 2 , a 1 and a 0 pins to provide the capability f o r addressing up to eight 1k/2k devices on a si ngle bus system (please see the device addressing section for further details) the ctk24bc04 uses the a 2 and a 1 inputs and a total of for 4k device m a y be addressed on a single bus system. the a 0 pin is not used, but should be grounded if possible. the ctk24bc08 only uses the a 2 input hardware addressing. on a single bus system , a total of two 8k devices m a y be addressed. the a 0 and a 1 pins are not used, but should be grounded if possible. t he ctk24bc16 does not use the device address pi ns, so only one device can be connected to a single bus system. therefore, the a 0 , a 1 , and a 2 pins are not used, but should be grounded if possible. write protect (wp) : the ctk24bc01/02/04/08/16 has a w r ite prot ect pin that provides hardware data protection. w h en connected to ground, the w r ite protect pin allows for norm al read/write operations. if the w p pin is connected to v cc , no data can be overwritten. memory organization the internal m e mory organization for the ctk24bc fam ily is arranged dif f erently for each of the d e nsities. the ctk24bc01, for instance, is internally organized as 16 pages of 8 bytes each and requires a 7-bit data word address. the ctk24bc16, on the other hand, is organized as 128 pages of 16 bytes each with an 11-bit data word address. the table below sum m arizes these differences. density # of pages bytes per page data word address length ctk24bc01 (1k) 16 pages 8 bytes 7 bits ctk24bc02 (2k) 32 pages 8 bytes 8 bits ctk24bc04 (4k) 32 pages 16 bytes 9 bits ctk24bc08 (8k) 64 pages 16 bytes 10 bits ctk24bc16 (16k) 128 pages 16 bytes 11 bits pin capacitance applicable over recommended operating range :t a =25 : , f=1mhz, v cc =+1.8v symbol test condition max unit condition c i/o input/output capacitance (sda) 8 pf v i/o =0v c in input capacitance (a 0 , a 1 ,a 2 , scl) 6 pf v in =0v not e : these param e t e rs are charact eri zed and not 100% t e st ed.
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 4/12 ctk24bc01-16q8 cy s t ek product s pecification dc characteristics applicable over recommended operating range: t a =-40~+85 , v cc =+1.8v~+5.0v (unless otherwise noted) parameter symbol condition min. typ. max. unit supply voltage v cc 1 1.8 - 5.5 v supply voltage v cc 2 2.7 - 5.5 v supply voltage v cc 3 4.5 - 5.5 v supply current v cc =5.0v i cc read at 100khz - 0.4 1.0 ma supply current v cc =5.0v i cc write at 100khz - 2.0 3.0 ma standby current v cc =1.8v i sb 1 v in =v cc or v ss - 0.6 3.0 a standby current v cc =2.5v i sb 2 v in =v cc or v ss - 1.4 4.0 a standby current v cc =5.5v i sb 3 v in =v cc or v ss - 5.0 18 a input leakage current i li v in =v cc or v ss - 0.2 5.0 a output leakage current i lo v out =v cc or v ss - 0.1 5.0 a input low level ( note 1 ) v il -0.6 - v cc 0.3 v input high level ( note 1 ) v ih v cc 0.7 - v cc +0.5 v output low level v cc =3.0v v ol 2 i ol =2.1ma - - 0.4 v output low level v cc =3.0v v ol 1 i ol =0.15ma - - 0.2 v note : v il and v ih max are reference only and are not tested. ac characteristics applicable over recommended operating range: t a =-40~+85 , v cc =+1.8v~+5.0v, c l =1 ttl gate & 100pf(unless otherwise noted) parameter symbol condition min. typ. max. unit clock frequency, scl f scl v cc =1.8v v cc =2.7~5.5v - - 100 400 khz clock pulse width low t low v cc =1.8v v cc =2.7~5.5v 4.7 1.2 - - s clock pulse width high t high v cc =1.8v v cc =2.7~5.5v 4.0 0.6 - - s noise suppression time (note 1) t i v cc =1.8v v cc =2.7~5.5v - - 100 50 ns clock low to data out valid t aa v cc =1.8v v cc =2.7~5.5v 0.1 0.1 - 4.5 0.9 s time the bus must be free before a new transmission can start (note 1) t buf v cc =1.8v v cc =2.7~5.5v 4.7 1.2 - - s start hold time t hd.sta v cc =1.8v v cc =2.7~5.5v 4.0 0.6 - - s start setup time t su.sta v cc =1.8v v cc =2.7~5.5v 4.7 0.6 - - s data in hold time t hd.dat v cc =1.8v v cc =2.7~5.5v 0 0 - - s data in setup time t su.dat v cc =1.8v v cc =2.7~5.5v 200 100 - - ns input rise time (note 1) t r v cc =1.8v v cc =2.7~5.5v - - 1.0 0.3 s input fall time (note 1) t f v cc =1.8v v cc =2.7~5.5v - - 300 300 ns
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 5/12 ctk24bc01-16q8 cy s t ek product s pecification ac characteristics(cont.) applicable over recommended operating range: t a =-40~+85 , v cc =+1.8v~+5.0v, c l =1ttl gate & 100pf(unless otherwise noted) parameter symbol condition min. typ. max. unit stop setup time t su.sto v cc =1.8v v cc =2.7~5.5v 4.7 0.6 - - s data out hold time t dh v cc =1.8v v cc =2.7~5.5v 100 50 - - ns write cycle time t wr v cc =1.8v v cc =2.7~5.5v - - 5 5 ms 5.0v, 25 , byte mode endurance (note 1) v cc =1.8v v cc =2.7~5.5v 1m 1m - - write cycles note: 1. this parameter is characterized and not 100% tested. device operation clock and data transitions : transitions on the sda pin should only occur when scl is low(refer to the data validity timing diagram in figure 3). if the sda pin changes when scl is high, then the transition will be interpreted as a start or stop condition. st ar t condition: a st ar t condition occurs when the sda transitions from high to low when scl is high. the st ar t signal is usually used to initiate a com m a nd(refer to the st ar t and st op definition timing diagram in fig 4) st op condition: a st op conditio n occurs wh en the sda transitions f r o m low to high when scl is high . (refer to th e st ar t and st op de finition tim ing diagram in fig 4) the st op command will pu t th e devic e into standby m ode after no acknowledgem ent is issued during the read sequence. acknow ledge: an acknowledgem e nt is sent by pulling the sda low to confirm that a word has been successfully received. all addresses and data words are serially transm itted to and from the eeprom in 8-bit words, so acknowledgements are usually issued during the 9 th clock cycle. standby mode: standby mode is entered when the chip is initially powered-on or after a stop command has been issued and any internal operations have been completed. memory reset: in the event of unexpected power or connecti on loss, a start condition can be issued to restart the input command sequence. if the device is currently in write cycle mode, this command will be ignored.
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 6/12 ctk24bc01-16q8 cy s t ek product s pecification bus timing figure 1. scl: serial clock, sda: serial data i/o write cycle timing figure 2. scl: serial clock, sda: serial data i/o n ote : 1. the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 7/12 ctk24bc01-16q8 cy s t ek product s pecification figure 3. data validity figure 4. start and stop definition figure 5. output acknowledge
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 8/12 ctk24bc01-16q8 cy s t ek product s pecification device addressing to enable the chip for a read or write operation, an 8-bit device address word followed by a start condition must be issued. the 1 st four bits of the device address word consist of a mandatory ?1010? pattern, while the 2 nd four bits depend on the particular density being used(refer to figure 6): in the 1k/2k chip, the next 3 bits should correspond to the hard-wired input a 2 , a 1 , and a 0 device address bits. in the 4k chip, the next 3 bits are the a 2 and a 1 device address bits and a m em o ry page address bit. the two device address bits must compare to their corresponding hard-wired input pins. in the 8k chip, the next 3 bits include the a 2 device address bit with the next 2 bits used for memory page addressing. the a 2 bit must compare to its corresponding hard-wired input pin. the 16k chip does not use any device address bits but instead the 3 bits are used for memory page addressing. figure 6. device address the memory page address bits , p 2 , p 1 , and p 0 are used to select the page in the array. p 2 represents the most significant bit, while p 1 and p 0 are considered the next most significant bits. the eight bit of the device address determines read or write operation. if the r/w bit is high, then a read operation is initiated. otherwise, if the r/w bit is low, then a write operation is started. after comparing the device address and finding a match, the eeprom device will issue an acknowledge- ment by pulling sda low. if the comparison fails, the chip will return to standby mode. figure 7. byte write
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 9/12 ctk24bc01-16q8 cy s t ek product s pecification figure 8. page write write operation byte/page write: if a write operation is entered (r/w =0) and an acknowledgement is sent, then the next sequence requires an 8-bit data word address. after an acknowledgeme nt is received from this word address, the 1 st byte of data can be loaded. the device will send an acknowledgement after each byte to confirm the transmission. to being the write cycle, a stop condition must be issued ( refer to figure 7). both byte and page write operations are supported, so the stop condition can be issued after the 1 st byte or the last byte in the page. when the stop condition occurs, an internal time is started, all inputs are disabled, and the eeprom will not respond to any more commands until the write cycle is completed. note: the number of bytes in a page depends on the density used. if 1k density is used, then the page size is 8 bytes. in contrast, if the 16k density is used, then the page size is 16 bytes. refer to the memory organization section for more details. the internal page counter is incremented after each byt e received, but the row location of the memory page will always remain the same. therefore the device will wrap around to the 1 st byte in the page after the last byte in the page is received. any further data loaded into the page buffer will overwrite the previous data loaded. acknowledge polling: after the stop condition is issued, the write cycle begins. acknowledge polling can be initiated by sending a start condition followed by the device address word. if the eeprom has completed the internal write cycle and returned to standby mode, the device will respond by sending back an acknowledgement by pulling the sda pin low. otherwise, the sequence will be ignored and no acknowledgement will be sent. read operations there are three types of read operations: current addr ess read, random address read, and sequence read. a random address read can be consider ed a current address read operation with an additional sequence in the beginning to load a different address into the internal counter. a sequential read occurs when subsequent bytes are clocked out after a current address read or random address read occurs.
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 10/12 ctk24bc01-16q8 cy s t ek product s pecification current address read : a current address read operation is initiated by issuing r/w=1 in the device address word(refer to figure 9). since the internal address counter maintains the last address incremented by one accessed during the last read or write operation, the internal address counter will always retain the last address incremented by one. random read : to access a different address location that the one currently stored in the internal counter, a random read operation is provided. the random read is actually a combination of a ?dummy? byte write sequence with a current address read command (refer to figure 10). the ?dummy? byte write loads a different address into the internal counter, and the da ta can then be accessed using the current address read. sequential read : in order to access subsequent data word afte r a current address read or random read has been initiated, the user should send an acknowledgement to the eeprom chip after ea ch data byte received. if an acknowledgement is not received, then the chip will not send any more data and expect a stop condition on the next cycle to reset back to standby mode(refer to figure 11). sequential reads can be used to perform an entire chip read. unlike the page write operation, the internal counter will increment to the next row after the last byte of the page has been reached. when the address reaches the last byte of the last memory page, the next address will increment to the 1 st byte of the 1 st memory page. once the memory address limit is reached, the data word address will ?roll over? and the sequential read will continue. when the microcontroller does not respond with a zero but does generate a following stop condition, the sequential read operation is terminated. figure 9. current address read
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 1 1/12 ctk24bc01-16q8 cy s t ek product s pecification figure 10. random read figure 11. sequential read ordering information ordering code package device function operating ranges ctk24bc01q8 1k bit(128 8) CTK24BC02Q8 2k bit(256 8) ctk24bc04q8 4k bit(512 8) ctk24bc08q8 8k bit(1024 8) ctk24bc16q8 sop-8 16k bit(2048 8) industrial (-40~+85 )
cys tech electronics corp. s pec. no. : c705q8 issued date : 2007.08.22 revised date : page no. : 12/12 ctk24bc01-16q8 cy s t ek product s pecification sop-8 dimension 8-lead so-8 plastic package cystek packa g e code: q8 marking: top view a b front view f c d e g part a i h j k o m l n rig ht side view part a 24bc date code memory: 1k: 01 2k: 02 4k: 04 8k:08 16k:16 *: typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1909 0.2007 4.85 5.10 i 0.0019 0.0078 0.05 0.20 b 0.1515 0.1555 3.85 3.95 j 0.0118 0.0275 0.30 0.70 c 0.2283 0.2441 5.80 6.20 k 0.0074 0.0098 0.19 0.25 d 0.0480 0.0519 1.22 1.32 l 0.0145 0.0204 0.37 0.52 e 0.0145 0.0185 0.37 0.47 m 0.0118 0.0197 0.30 0.50 f 0.1472 0.1527 3.74 3.88 n 0.0031 0.0051 0.08 0.13 g 0.0570 0.0649 1.45 1.65 o 0.0000 0.0059 0.00 0.15 h 0.1889 0.2007 4.80 5.10 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0 important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .

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